1. Field of the Invention
The present invention relates to a semiconductor device having a protection element that prevents a breakdown caused by a surge voltage such as electrostatic discharge (hereinafter referred to as ESD).
2. Description of the Related Art
In one example, a conventional semiconductor element is known to include a protection element, which will be described below. FIG. 5 is a cross-sectional view illustrating the conventional semiconductor device.
As shown in FIG. 5, a P type epitaxial layer 42 is formed on a P type semiconductor substrate 41. On the epitaxial layer 42, an N type diffusion layer 43 is formed as a forming region of a lateral MOSFET (metal-oxide-semiconductor filed effect transistor) 49. On the N type diffusion layer 43, a P type diffusion layer 44 is formed as a back-gate region. On the P type diffusion layer 44, an N type diffusion layer 45 is formed as a source region, and an N type diffusion layer 46 is formed as a drain region. Moreover, on the P type diffusion layer 44, a gate oxide film 47 and a gate electrode 48 are formed. Thus, the lateral MOSFET 49 is formed. Note that a diffusion depth of the N type diffusion layer 43 is L1.
In addition, a protection element 50 is formed above the substrate 41 in order to protect the lateral MOSFET 49 from the ESD surge. The structure of the protection element 50 is described below. An N type diffusion layer 51 is formed in the epitaxial layer 42, the N type diffusion layer 51 having the same or slightly lower impurity concentration than the N type diffusion layer 43. A diffusion depth of the N type diffusion layer 51 is L2, and a relation of L2≦L1 is satisfied. An N type diffusion layer 52 is also formed in the epitaxial layer 42 so as to surround the N type diffusion layer 51. The N type diffusion layer 52 has an impurity concentration higher than the N type diffusion layer 51. A diffusion depth of the N type diffusion layer 52 is L3, and a relation of L3>L2 is satisfied. P type diffusion layers 53 and an N type diffusion layer 54 are formed in the N type diffusion layer 51. The diffusion layers 53 and 54 are shorted by an emitter electrode 55. A bottom surface electrode 56 is formed on the bottom surface of the substrate 41.
In the above structure, the protection element 50 includes a PNP transistor Tr3 and a PN diode D3 combined with each other. The PN diode D3 in the protection element 50 operates in avalanche mode prior to the lateral MOSFET 49. Then, an avalanche current causes the PNP transistor Tr3 to operate. This operation prevents the lateral MOSFET 49 from being destroyed by the ESD surge. This technology is described for instance in Japanese Patent Application Publication No. 2005-235844 (pages 5-7, FIG. 1).
In the conventional semiconductor device, the protection element 50 having the structure different from that of the lateral MOSFET 49 is formed to protect the lateral MOSFET 49 from the ESD surge. The protection element 50 and the lateral MOSFET 49 are formed above the same substrate 41. As described above, the N type diffusion layer 52 is formed so that an avalanche voltage of the PN diode D3 of the protection element 50 may be lower than an avalanche voltage of the lateral MOSFET 49.
However, in the conventional semiconductor device, the N type diffusion layer 43 and the N type diffusion layer 52 are formed in different process steps and on different conditions. The structure that determines an avalanche voltage of the lateral MOSFET 49 and the structure that determines an avalanche voltage of the protection element 50 do not share the same structure. Accordingly, there occurs a problem that variations in manufacturing conditions, such as mask misalignments and a time lag in thermal diffusion, cause the avalanche voltage of the lateral MOSFET 49 to be lower than the avalanche voltage of the PN diode D3 in the protection element 50, and that the lateral MOSFET 49 is consequently destroyed by the ESD surge.